1. Field of the Invention
This invention relates to an arrangement (apparatus and method) for storing, indicating or producing signals, and an arrangement for storing and indicating signals related to internal information of a computer stored in a random access memory, a register and the like together with input and output signals of the computer, a method of producing logical signals, an apparatus for recording signals and an apparatus for recording and producing signals, all of which are suitable for use in an engine control simulator for analyzing abnormal conditions and the like in an engine electronic control system using a microcomputer.
2. Description of the Related Art
In order to analyze an engine control system that in many ways acts as a plurality of feedback control systems (for controlling various aspects of engine operation based on sensed conditions), it is necessary to measure various sensor output signals and engine parameters at specific times and to know precisely the time at which a particular measurement was taken. In other words, many signals must be synchronized in the sense of knowing their corresponding timing relations.
In consequence, it may be proposed that not only the input and output signals of the computer but also the internal information of the computer, which have been stored in the random access memory, the register and the like are stored and indicated simultaneously.
However, when data obtained by measuring the input and output signals of the computer and storing the same are not synchronized with data obtained by reading the internal information of the computer and storing the same, the measurement and analysis cannot be accurately performed. It is not certain what values the computer has processed as input signals, how the computer has processed the input signals to calculate output values, whether the calculated values accurately correspond to the output signals, whether the timing between the calculated values and the output signal are accurate and so forth.
Furthermore, in order to analyze the aforesaid engine control system, it is necessary to have a simulation function for reproducing actual signals of the engine to reproduce troubles of rare occurance. In other words, it is necessary that signals measured and stored can be reproduced in waveforms indentical with the signals measured.
A known method for recording a plurality of waveforms of logic signals as time functions is to use a multipoint recorder and to record the signals simultaneously on a recording paper. This method works well for analogue signals, however, it is inconvenient for numerical analysis, because the recorded signals are not codified values.
Therefore, when a plurality of waveforms of logical signals are to be codified and recorded, the firstly proposed method is one, in which samples are taken at predetermined time intervals shorter than a waveform period of the logical signal having the shortest cycle out of the plurality of logical signals and the logical level thereof is codified for use by a logic analyzer. More specifically, as shown in FIG. 20 for example, samplings are taken of four signal waveforms S1-S4 shown in FIGS. 20(a)-20(d) by a predetermined interval shown in FIG. 20(e) such as t1-t12. Then, the logical levels at the sample times are recorded as 0 or 1 as shown in FIG. 21. Signals S1-S4 are associated with respective bits, whereby recording is performed in time series at every sampling time such as the times of t1-t14. However, this arrangement is not practical, particularly for engine analysis. In such analysis, there are multiple channels of logic signals and the frequency of occurrence of edges (changes of logic level) is low. The time interval between transitions of logic signal level becomes long with respect to the sampling period. Signal levels that do not vary in level from one measuring (sampling) time to the next are recorded at each measuring time. Thus the same signal level is recorded many times in the data accumulating area. When there are many channels of data to be recorded, the amount of data accumulated becomes enormous. This wastes a tremendous amount of data accumulating capacity. It is also difficult to timely transfer such huge amounts of data to a storage medium. For example, when input and output signals of 64 channels are measured at a time interval of required time accuracy of 5 microsecond (corresponding to 0.2.degree. CA in a spark advance of 6000 rpm), the amount of data produced reaches 1.6 megabyte/sec, which exceeds the data transfer capability of a typical minicomputer, e.g. 600 kilobyte/sec. Further, if the waveform is not regular, then the cycle of the data sampling does not coincide with the time of the level transition, whereby it becomes difficult to reproduce the recorded input and output signals with high accuracy.
A method of obviating the above-described disadvantages is set forth in Japanese Patent Application No. 26722/1983 (laid open 9/1/85 and assigned to the same assignee as this application). A counter for counting clock signals of a predetermined period is actuated in synchronism with a control signal indicating the start of recording. The logical level of waveforms of a plurality of logical signals is monitored, and when a waveform edge portion indicating a transition of the logical level is detected, a signal label specifying the signal which has produced the aforesaid waveform edge portion, a logical level after the transition and edge detection data formed by a value of the aforesaid counter at the time of detecting the edge portion are recorded.
In other words, when the signal waves S1-S4 as shown in FIG. 20 are to be recorded by this method, the counter is actuated simultaneously with the start of recording of the logical signal, and the current time is indicated by counting the clock signals of the predetermined interval. When the waveform edge portions indicating the transitions of the logical signal with the respective logical signals are detected, i.e. at the time T1 of the signal S1, a data block 101 shown in FIG. 22 is outputted. One data block is constituted by a two word arrangement for example and a first word includes a label S1 specifying the logical signal in which the edge is detected and a value 1 of the logical level after the transition. A second word includes a transition time T1 of the logical level, i.e. the value of the counter at that time. One data block being of the above-described arrangement constitutes one edge detection data. Subsequent detections of the waveform edge portion are made at the time T2 of the signals S1 and S3. When two or more waveform edge portions are detected in two or more logical signals at the same time as described above, such an arrangement is adopted that the edge detection data are recorded in a preset order of priority, e.g. an order from a signal being junior in number to senior. In consequence, the edge detection data are recorded in the order of the logical signals S1 to S3 as shown in data blocks 102 and 103. More specifically, the data block 101 includes the signal label S1 specifying the logical signal, a logical level 0 after the transition and the counter value T2 showing the time then. Similarly, the data block 103 includes the signal label S3 specifying the logical signal, a logical label 1 after the transition and the time T2 then. The edge detection data are successively recorded as described above.
In consequence, according to this method, the time, at which the logical levels are caused to transit, are recorded and the waveforms can be accurately duplicated and the data accumulating area can be reduced as much as possible.
There has been proposed no effective method of producing logical signals. For example, the reverse utilization of a data sampling method of a clock interval adopted in the aforesaid logic analyzer, for reproducing data at a predetermined interval is disadvantageous in producing signals with high time accuracy due to a low data transfer capability.
Further, in analyzing the aforesaid engine control system, as proposed by the applicant in Japanese Patent Application No. 26722/1983 for example, such a proposal may be made that the actual signals of the engine are recorded by use of a digital signal converter for detecting the transition time of the logical level of digital signals and the logical level after the transition and converting the same into data for recording, and an analogue-digital converter (hereinafter referred to as an "A/D converter") for converting an analogue signal into a digital signal to produce data for recording.
In order to duplicate the troubles of rare occurrence, it is necessary that a simulation function for reproducing the actual signals of the engine is provided, so that the measured and recorded signals can be reproduced in the waveforms indentical with those of the measured signals. For this purpose, it may be proposed that, in addition to the digital signal converter and the A/D converter as aforesaid, there are provided:
a digital signal producer for changing the logical level of the produced digital signal so that the logic level of the produced digital signal after transition is made to be the logic level of the aforesaid data after transition in accordance with the transition time of the logical level of the data for producing the digital signals and the logical level after the transition, both of which are read out of a storage device at the time, when the current time after the start of production of signals coincides with the aforesaid transition time of the logical level and
a digital-analogue converter (hereinafter referred to as a "D/A converter") for returning the digital data for producing an analogue signal, which is read out of the storage device, to an analogue signal to produce the analogue signal.
However, when clocks for exclusive use are provided on the digital signal converter, the A/D converter, the digital signal producer and the D/A converter, respectively, as usually adopted to prevent the delay in transmission, even if all of these clocks are synchronized at the time of the start of recording or reproducing, and the recording and reproducing of the actual signals of the engine are started at the same time, a shift in time occurs between the digital signal and the analogue signal due to a difference between the clocks during the recording or reproducing of scores of minutes, so that it becomes disadvantageously impossible to accurately record or reproduce the actual signals of the engine.
More specifically, when knock signals of the engine are recorded for example, it is necessary to record output waveforms of a knock sensor as shown in FIG. 23(A) in analogue, and also digitally record a masking signal as shown in FIG. 23(B) being closed at a position not close to the ignition timing, for preventing an error in judgment of knocking due to a cause other than the knocking. In this case, when the clock of the output waveform of the knock sensor as being an analogue signal accurately coincides with the clock of the making signal as being a digital signal, then both signals can be accurately recorded or reproduced. However, when the clock of the analogue signals is independently formed of the clock of the digital signals and the frequencies therebetween are shifted, the both signals become out of synchronism, the masking signal is delayed as indicated by broken lines in FIG. 23(B) for example, whereby such an unusual waveform is obtained that the ignition timing is advanced at the succeeding ignition after an occurrence of a knocking, thus presenting a disadvantage that an accurate recording or reproducing cannot be performed.